The present invention generally relates to integrated circuit memory devices, and more specifically, to improvements to 4 transistor (4T) static random access memory (SRAM) bitcell retention.
Memory devices are commonly employed as internal storage areas in a computer or other electronic equipment. One specific type of memory used to store data in a computer is random access memory (RAM). RAM is typically used as main memory in a computer environment and is generally volatile in that once power is turned off, all data stored in the RAM is lost.
An SRAM is one example of a RAM. An SRAM has the advantage of holding data without a need for refreshing. A typical SRAM device includes an array of individual SRAM cells or bitcells. Each SRAM cell is capable of storing a binary voltage value that represents a logical data bit (e.g., “0” or “1”). One existing configuration for an SRAM cell includes a pair of cross-coupled devices such as inverters. The inverters act as a latch that stores the data bit therein as long as power is supplied to the memory array. In a conventional six-transistor (6T) cell, a pair of access transistors or pass gates (when activated by a word line) selectively couples the inverters to a pair of complementary bit lines (i.e., a bit line true and bit line complementary). Other SRAM cell designs can include a different number of transistors (e.g., 4T, 8T, etc.), which can have different advantages and drawbacks.